1. Field of the Invention
This invention relates to a liquid crystal display device, and more particularly, to an apparatus and a method of driving liquid crystal display device capable of reducing electromagnetic interference (EMI) by minimizing the number of data transitions.
2. Description of the Related Art
In general, a liquid crystal display (LCD) controls light transmittance of liquid crystal cells in accordance with video signals to thereby display a picture. Such devices have been implemented in an active matrix LCD having a switching device for each cell. They have been used as a display device, such as a monitor for a computer, office equipments, a cellular phone and the like. The switching device for the active matrix LCD device employs a thin film transistor (TFT).
FIG. 1 schematically illustrates a related art apparatus for driving an LCD device.
Referring to FIG. 1, the related art LCD driving apparatus includes: a liquid crystal display panel 2 having a plurality of liquid crystal cells Clc arranged in a matrix at the crossings of data lines DL and gate lines GL; a data driver 4 for applying data signals to the data lines; a gate driver 6 for applying scanning signals to the gate lines GL; and a timing controller 8 for controlling the data driver 4 and the gate driver 6 using synchronizing signals H, V and DE supplied from a system 10.
The liquid crystal display panel 2 includes the liquid crystal cells Clc arranged in a matrix at the crossings between the data lines DL and the gate lines GL. A thin film transistor TFT provided at each liquid crystal cell Clc applies a data signal from the data lines DL to the liquid crystal cell Clc in response to a scanning signal from the gate lines GL. Further, each liquid crystal cell Clc is provided with a storage capacitor Cst. The storage capacitor Cst constantly keeps a voltage of the liquid crystal cell Clc.
The data driver 4 converts digital video data R, G and B into analog gamma voltages (i.e., data signals) corresponding to values of gray levels in response to a data control signal DCS from the timing controller 8, and applies the analog gamma voltages to the data lines DL.
The gate driver 6 sequentially applies a scanning pulse to the gate lines GL in response to a gate control signal GCS from the timing controller 8 to select each horizontal line of the liquid crystal display panel 2 to which the data signals are applied.
The system 10 applies vertical/horizontal signals V and H, clock signals DCLK and a data enable signal DE to the timing controller 8.
The timing controller 8 generates the data control signals DCS and the gate control signals GCS for controlling the gate driver 6 and the data driver 4 using the vertical/horizontal synchronizing signals V and H and the clock signal DCLK input from the system 10. The timing controller 8 recovers the data supplied from the system 10 as parallel data to apply the recovered parallel data to the data driver 4.
As described above, the timing controller 8 supplies data for one pixel unit. For example, data for one pixel unit may be 18-bit data: 6-bits for each color red (R), green (G), and blue (B). The timing controller 8 in this example provides the data to the data driver 4 by using 18 data lines, one for each bit. However, when the data of one pixel unit is supplied from the timing controller 8 to the data driver 4, then significant electromagnetic interference (EMI) occurs during the transition of data.
TABLE 1R[0:5]G[0:5]B[0:5]Pn000000000000000000Pn + 1111111111111111111
For instance, as illustrated in Table 1, if all of the current pixel data Pn have ‘0’ bits and all of following pixel data Pn+1 have ‘1’ bits, then a data transition occurs at every bit, thereby creating significant EMI. Furthermore, this phenomenon becomes more serious as the size and resolution of the liquid crystal panel 2 is increased. For example, if 24-bit data (8-bit for each of R, G and B) is used for the data of one pixel unit, even more EMI occurs as the number of bits transmitted from the timing controller 8 to the data driver 4 increases.
Thus, a driving apparatus as illustrated in FIG. 2 has been proposed in the related art in order to prevent the generation of the EMI.
FIG. 2 schematically illustrates an LCD driving apparatus according to another embodiment of a related art. In FIG. 2, constituent elements having the same functions as those of FIG. 1 will have the same reference numerals as those of FIG. 1 and therefore detailed explanations therefor will be omitted for the sake of simplicity.
Referring to FIG. 2, the related art LCD driving apparatus includes: a liquid crystal display panel 2 having a plurality of liquid crystal cells Clc arranged in a matrix at the crossings of data lines DL and gate lines GL; a data driver 4 for applying data signals to the data lines; a gate driver 6 for applying scanning signals to the gate lines GL; and a timing controller 12 for controlling the data driver 4 and the gate driver 6 using synchronizing signals H, V and DE supplied from a system 10.
The timing controller 12 generates the data control signals DCS and the gate control signals GCS for controlling the gate driver 6 and the data driver 4 using the vertical/horizontal synchronizing signals V and H and the clock signal DCLK input from the system 10. The timing controller 12 recovers the data supplied from the system 10 as parallel data to apply the recovered parallel data to the data driver 4. Further, the timing controller 12 includes a mode controller 14 for minimizing the number of data transitions.
The mode controller 14 compares a data transition state of the next pixel data to be supplied to the data driver 4 with that of current pixel data being supplied to the data driver 4. That is, the mode controller 14 compares each bit of the next pixel data Pn+1. with each bit of the current pixel data Pn to detect the number of data transitions such as ‘0→1’ or ‘1→0’ and inverts or does not invert the data to be output pursuant to the number of the detected data transitions.
Substantially, the mode controller 14 calculates the number of data transitions and determines whether the number of the calculated data transitions exceeds a threshold value, for example, 9 bits being a half of 18 bits of a total transmitted quantity. Furthermore, whenever the data transition quantity exceeds the threshold value, the mode controller 14 inverts logical values of a mode control signal REV and the next pixel data to be supplied to supply the inverted logical values to the data driver 4.
TABLE 2Data transitionSignalR[0:5]G[0:5]B[0:5]quantityREVPn000000000000000000 0lowPn + 111111111111111111116highPn + 200000000000000000016lowPn + 300110111111100111012highPn + 4001101000000001110 6high
For instance, as illustrated in Table 2, if all of the current pixel data Pn have ‘0’ bits and all of the next pixel data Pn+1 have ‘1’ bits, then 16 data transitions occurred. In this case, because the data transition becomes more than the threshold value (that is, 9), the logical value of the mode control signal REV is inverted and the next pixel data Pn+1 has a data string of ‘000000 000000 000000’. At this time, the data driver 4 inverts the data Pn+1 inverts in response to the mode control signal REV to generate a data string of ‘111111 111111 111111’, that is, the original data is recovered).
As described above, the related art LCD driving apparatus compares the current pixel data with the next pixel data and inverts or does not invert the data to be output. Accordingly, it is possible to prevent the generation of high EMI. However, because the related art LCD driving apparatus performs the simple comparison of the current pixel data and the next pixel data to invert or not invert the data, there is a limit to reduce the number of data transitions. In other words, the related art has a limit to reduce the EMI.